Gabriel West

Computer Engineering, University of Illinois Urbana-Champaign (expected May 2029). Computer architecture, FPGA, firmware, and high-performance systems software. gwest9@illinois.edu · github.com/gw12343 · llms.txt · llms-full.txt · Resume (PDF)

Seeking internships in computer architecture, FPGA, firmware, and high-performance systems software.

Projects

1. fpga-builder: Visual Verilog Generator — C++ node-graph editor that compiles digital logic to synthesizable Verilog. Used to port a previously designed 32-bit CPU onto a Nexys A7 at 50 MHz with zero manual HDL edits. markdown
2. Custom 32-bit CPU and toolchain — Original 32-bit ISA: Logisim CPU, Java two-pass assembler, cycle-accurate C emulator, then the same design on FPGA running Snake on a Nexys A7 over UART. markdown
3. cpp-engine: 3D OpenGL game engine — From-scratch C++ engine with an ImGui editor, Jolt physics, Ozz skeletal animation, Effekseer particles, OpenAL, and Lua via Sol3. markdown
4. Autonomous ROS2 robot — Jetson Orin Nano robot with ROS2 Nav2, RPLiDAR SLAM, Llama 3 voice commands via NVIDIA Riva, and an expressive eye display. markdown

Recordings described in text

Typical language-model crawlers cannot play MP4s. Each project page includes a prose description of what is on camera, written so a model that only reads HTML still sees the hardware evidence.